1. Field of the Invention
This invention relates to a semiconductive GaAs wafer and, in particular, a semiconductive GaAs wafer that the incidence of a slip dislocation can be reduced in heat treatment such as an activation annealing after an ion implantation to be conducted in the process of fabricating an electronic device by using the GaAs wafer. Also, this invention relates to a method of making the semiconductive GaAs wafer.
2. Description of the Related Art
Semiconductive GaAs wafers are made generally by the Liquid Encapsulated Czochralski (LEC) method, or the vertical melt method such as vertical bridgeman (VB) and vertical gradient freeze (VGF).
A method of making a GaAs single crystal by the LEC method will be explained below referring to FIG. 1.
A GaAs single crystal growth equipment 1 for the LEC method comprises a chamber 2 which composes a furnace body, a pulling shaft 3 for pulling the crystal, a crucible 5 which is a container for raw material, and a crucible shaft 4 which supports the crucible 5.
In operation, Ga, As and boron trioxide 6 which prevents the volatilization of As are charged in the crucible 5 which is generally made of PBN (pyrolytical boron nitride). Then, the crucible 5 is placed in the chamber 2. A seed crystal 7 as a crystal source is attached to the tip of the pulling shaft 3. The seed crystal 7 generally has a (100) plane to face the GaAs melt.
After the raw materials are placed in the chamber 2, the chamber 2 is vacuumed and then charged with inert gas. Then, a resistance heater 8 built in the chamber 2 is fed with current to increase the inside temperature of the chamber 2 so that Ga and As are reacted to synthesize GaAs. Then, by further increasing the temperature, GaAs melt 9 is obtained. Then, the pulling shaft 3 and the crucible shaft 4 are rotated inversely to each other. In this state, the pulling shaft 3 descends until the seed crystal 7 attached to the tip thereof contacts the GaAs melt 9. Then, the pulling shaft 3 is raised at a constant rate while lowering gradually the setting temperature of the resistance heater 8. Thereby, the crystal diameter increases gradually from the seed crystal to form a crystal shoulder. When a target crystal outside diameter is obtained after forming the crystal shoulder, its shape control is conducted to keep the outside diameter to obtain a GaAs single crystal 10.
Next, a method of making a GaAs single crystal by the vertical melt method will be explained below referring to FIG. 2.
A GaAs single crystal growth equipment 21 for the vertical melt method (such as the VB method or VGF method) comprises a chamber 22 as a furnace body, and a crucible shaft 24 which supports a crucible 25 which is a container for raw materials.
In operation, GaAs polycrystal and boron trioxide 26 which prevents the volatilization of As are charged in the crucible 25 which is generally made of PBN (pyrolytical boron nitride) Then, the crucible 25 is placed in the chamber 22. A seed crystal 27 as a crystal source is attached inside a reduced diameter part at the bottom of the crucible 25. The seed crystal 27 generally has a (100) plane to face the GaAs melt.
Then, the chamber 22 is vacuumed and then charged with inert gas. Then, a resistance heater 28 built in the chamber 22 is fed with current to increase the inside temperature of the chamber 2 while forming a temperature gradient that temperature increases from the bottom toward the top. Thereby, the GaAs polycrystal is melted to have GaAs melt 29. Then, the seeding is conducted such that the furnace temperature is further increased until the GaAs melt 29 contacts the seed crystal 27 attached to the bottom of the crucible 25.
Then, in case of the VB method, the crucible 24 descends at a constant rate while keeping the setting temperature of the resistance heater 28 such that the GaAs melt 29 is solidified from the seed crystal 27 to obtain a GaAs single crystal. In case of the VGF method, after the seeding, the setting temperature of the resistance heater 28 lowers at a constant rate without moving the crucible shaft 24 such that the GaAs melt 29 is solidified from the seed crystal 27 to obtain a GaAs single crystal.
The LED method and the vertical melt method (VB or VGF) have the following advantage and disadvantage.
In case of the LEC method, the crystal growth is conducted under the condition of a steep temperature gradient. Therefore, the LEC method is suited to increase the rate of crystal growth since the cooling of crystal can be easy conducted, and it is very advantageous in throughput. However, due to the crystal growth in the steep temperature gradient, the LEC method tends to have a dislocation density in wafer plane (herein also called ‘etch pit density’ (EPD)) higher than the VB and VGF methods such that its average in-plane dislocation density is 50,000 to 100,000/cm2 for a wafer with a diameter of φ15.24 cm (=6 inches). Meanwhile, the influence of the dislocation density in a semiconductive GaAs wafer on the characteristics of an electronic device is still unknown. Thus, a conclusion is not obtained that a low dislocation density results in a good characteristic.
In case of the VB and VGF methods, the crystal growth is conducted under the condition of a gradual temperature gradient. Therefore, in contrast to the LEC method, the VB and VGF methods are not suited to increase the rate of crystal growth, and they are not advantageous in throughput. However, they are suited to lower its dislocation density in wafer plane (i.e, its average in-plane dislocation density is about 10,000/cm2 for a wafer with a diameter of φ15.24 cm (=6 inches).
On the other hand, the semiconductive GaAs wafer is used as a substrate material for electronic devices that require a high-speed operation and low power consumption. The semiconductive GaAs wafer for an electronic device's substrate supplied to an electronic device manufacturer is subjected to annealing (thermal treatment) such as activation annealing after ion implantation in the process of fabricating the electronic device.
The ion implantation is intended to enhance the conductivity of a wafer by implanting, e.g., Si ion onto the GaAs wafer. However, in the ion implantation, the lattice arrangement of crystal must be distorted so that the conductivity cannot be enhanced sufficiently. Thus, the activation annealing is conducted to rearrange suitably the crystal lattice.
The annealing is conducted independently under the conditions of each electronic device manufacturer. In general, it is conducted such that the wafer is rapidly heated to about 500 to 900° C. and then cooled rapidly.
In the annealing techniques, an attempt is conducted that a GaAs crystal wafer made by the vertical melt method is used as a substrate for the ion implantation since it has a low dislocation density and residual strain as compared to that made by the LEC method (see, e.g., JP-A-11-268997). However, when a crystal is actually made by the vertical melt method in mass production process, the crystal may have unstable characteristics rather than GaAs crystal (LED crystal) made by the LEC method. Further, when conducting the same heat treatment as conducted for the GaAs crystal made by the LEC method to the GaAs crystal made by the vertical melt method, especially the crystal with a diameter of more than 7.62 cm (=3 inches) may have an increased dislocation density and residual strain and have a uniformity mechanism different from the LEC crystal. Thus, JP-A-11-268997 discloses a method that a high-quality GaAs wafer practically usable for the device fabrication can be obtained by specifying the manufacturing conditions of GaAs crystal and the crystalline characteristics to have more stable and uniform electrical characteristics, and optimal heat treatment conditions.
However, the conventional methods have the following problems.
In fabricating an electronic device by using as its substrate the GaAs crystal made by the LEC method or the vertical melt method (VB or VGF), a slip dislocation may be generated at the GaAs wafer in the process of activation annealing after the ion implantation. Therefore, the device cannot be used as a product.
The main reason for generating the slip dislocation can be nonuniformity of temperature in wafer plane during the annealing. In this regard, each electronic device manufacturer tries to improve the annealing technique.
However, since in recent years the diameter of wafer is increased such that the mainstream diameter of GaAs wafer changes from conventional one, φ10.16 cm (=4 inches) to φ15.24 cm (=6 inches), a high-level control is needed for uniformity of temperature in wafer plane during the annealing than before. Thus, the uniformity of temperature in wafer plane is more important problem than before.
JP-A-11-268997 tries to use the GaAs crystal wafer made by the vertical melt method as a substrate for the ion implantation since it has a low dislocation density and residual strain as compared to that made by the LEC method.
However, as described earlier, the crystal made by the vertical melt method may have unstable characteristics rather than GaAs crystal (LED crystal) made by the LEC method. Further, the crystal made by the vertical melt method is not suited to the same heat treatment as conducted for the GaAs crystal made by the LEC method. Therefore, optimal heat treatment conditions needs to be further developed.
Further, the most important point is that even when the crystal made by the vertical melt method has a residual strain lower than the LEC crystal, it is not directly established that the former can offer a low slip dislocation. As the result of the inventors' researches, the slip dislocation after the activation annealing is not caused by only the residual strain.